Photo credit: www.techradar.com
AMD’s MI400 APU Set for 2026 Release, Enhancing AI and HPC Capabilities
New chip design features expanded density and potential FPGA integration
AMD is gearing up for the launch of its Instinct MI400 APU, anticipated in 2026. This new advanced processing unit aims to cater to the demands of artificial intelligence (AI), machine learning, and high-performance computing (HPC) tasks. It is expected to leverage AMD’s innovative chiplet-based modular design, increasing computational density and power efficiency while enhancing scalability.
The MI400 may play a critical role in upcoming supercomputing initiatives, potentially succeeding the El Capitan project. However, AMD has confirmed that it will utilize the upcoming CDNA “Next” architecture, leaving some details still under wraps.
Insights into the MI400’s structure emerged from a patch concerning the MicroEngine Scheduler (MES) v12, which was highlighted by Coelacanth’s Dream and echoed by VideoCardz.
The findings reveal that the MI400 is expected to feature two Active Interposer Dies (AIDs), each housing four Accelerated Compute Dies (XCDs), totaling eight XCDs. This configuration effectively doubles the XCD count per AID compared to the previous MI300 model. By concentrating more compute dies into fewer interposers, AMD aims to minimize latency and enhance efficiency, which are crucial for demanding AI and HPC applications.
Nonetheless, as pointed out by Coelacanth’s Dream, the MI400’s architecture may mirror that of the MI300, potentially allocating some AIDs to CPU tasks rather than exclusively for accelerators. This could limit the maximum number of available XCDs in certain configurations to four, which might reduce the overall XCD numbers compared to previous models like the MI300A APU.
A noteworthy feature of the MI400 is the introduction of the Multimedia IO Die (MID), which will handle tasks related to memory control, media processing, and interface management. This separation allows the compute dies to concentrate more fully on processing activities. The architecture suggests the inclusion of up to two MIDs, likely assigning one to each AID.
Additionally, this could mark AMD’s first foray into integrating Versal/Xilinx FPGA technology into its accelerator framework. In 2022, AMD disclosed plans to infuse Xilinx’s FPGA-powered AI inference capability into its CPU range, which might also point towards a potential Alveo series data center acceleration card.
Further patches mentioned a Register Remapping Table (RRMT), which would enable firmware to manage register transactions directed to particular AIDs, XCDs, or MIDs.
While AMD has yet to unveil any official specifications or designs for the MI400 series, anticipation continues to grow with the expected release in 2026. The forthcoming launch of the Instinct MI350 series, based on CDNA 4 architecture, will likely pave the way for additional insights into the MI400’s capabilities.
You might also like
Source
www.techradar.com